Figure 1: Overall Block Diagram The goal of this project is to provide you with a more practical hands-on approach to computer architecture design problems. The processor complex you will be designing is a 32-bit version of the MIPS processor; however, the instruction set will be a small subset of the actual MIPS ISA. You should implement the end to end operation of the complex utilizing the VHDL hardware descriptive language. You may use any constructs within the VHDL language, however, the design must be of your own. Copying of any form from any other student or any internal or external sources is illegal and will not be accepted. The processor supports the three instruction formats: R-format, I-format, and J-format as described in the textbook and lectures. The total set you need to design is the core set as above + a custom set designated for you as follows.
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2. Implementation Details
2. 1 CPU: You need to treat the CPU as a block diagram and show only the inputs, outputs, and changes in the Register File. Note that all the source values for the instructions are derived from the CPU registers and immediate value in the instruction itself. The results will also be stored in the register except for the store instruction. For both load and store instructions, ALU operation is needed for address calculation. You need not simulate the detailed internal operation of the CPU complex.
2. 2. Bus Used only for the transfer of words and blocks. The bus (between cache and memory) has the following specifications: Bandwidth of 32 words/cycle.
2. 3. Cache/Bus/Memory Specifications The focus of the report is on the cache operation. The cache has the following specifications 1.
All parameters must be defined as variables (or data inputs) so that different parameters can be used for testing your code.
You should annotate your code with appropriate/sufficient comments so that the code is self-explanatory.
You may use additional meaningful assumptions and state them clearly in your report.
Section 5 provides some useful hints for cache operation.
An overview of your design Appropriate sections to convey your report A discussion on how you tried to optimize your design A discussion on any improvements or additional features made to your design A discussion on what does not work correctly in your design An overview block diagram of your design. A sample simulation of your design that is annotated to show its correct operation. Copying code will not be acceptable. Any code copied will automatically result in a 0 for your project and may be subject to additional disciplinary action.
Start the project right away Good luck and have fun 5 Hint: Basic operations are summarized in the following. Please note that you need to modify it appropriately to account for placement/replacement, dirty bit status, write strategies, write miss strategies, etc.
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